A Single-Chip 2.5-Gb/s Burst-Mode Optical Receiver

IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 23, NO. 2, JANUARY 15, 2011 85

With Wide Dynamic Range
Sang-Heung Lee, Jongdeog Kim, Quan Le, Munseob Lee, Haecheon Kim, and Chang-Su Park

Abstract—

In this letter, a new burst-mode optical receiver with burst detection function is proposed and a single-chip 2.5-Gb/s burst mode optical receiver has been fabricated using 0.25- m SiGe bipolar complementary metal–oxide–semiconductor (BiCMOS) technology. The single-chip optical receiver

has high sensitivity and wide dynamic range for various classes of power budges required in 10-Gigabit-capable passive optical network (XG-PON1) (2.5-Gb/s upstream and 10-Gb/s downstreamdata rates). For the 2.5-Gb/s burst-mode data streams, sensitivity and overload were 32 and 4 dBm at a bit-error rate of �� �� ,

respectively, resulting in a dynamic range of 28 dB.

Index Terms—Automatic offset cancellation, burst-mode optical

receiver, gigabit-capable passive optical network (GPON), transimpedance

amplifier.

I. INTRODUCTION

GIGABIT-CLASS passive optical networks (PONs)

such as Gigabit-capable PON (GPON) and Ethernet

PON (EPON) are being widely developed as an economical

solution for attractive triple-play services. With the continuously

increasing bandwidth demand for future broadband

services, standardization efforts toward a next-generation PON

(NG-PON) are actively in progress for 10-Gigabit-class PONs,

10G-EPON by the IEEE 802.3av Task Force and 10-Gigabit-capable

PON (XG-PON) by the Full Service Access Network

(FSAN) NG-PON Task Group.

To realize the 10-Gigabit-class PONs, one of the key components

for higher speed upstream transmission is the burst-mode

optical receiver in the optical line termination (OLT). The

timing specification of GPON is much stricter than that of

EPON, which makes it difficult to realize a burst-mode optical

receiver for a higher data rate. Thus, XG-PON1 for 2.5 Gb/s

upstream and 10 Gb/s downstream data rates, as a first standard

for post-GPON, has been accepted for G.987 document series

in ITU-T Study Group 15.

The received signal power at the OLT may be varied drastically

due to different path loss between the optical network

units (ONUs) and the OLT. It imposes several design challenges

Manuscript received September 19, 2010; revised October 24, 2010; accepted

October 30, 2010. Date of publication November 11, 2010; date of current version

December 30, 2010. This work was supported by R&D Programs funded

by the Korean Government.

S.-H. Lee, J. Kim, Q. Le, M. Lee, and H. Kim are with the Electronics and

Telecommunications Research Institute, Yuseong-gu, Daejeon 305-700, Korea

(e-mail: shl@etri.re.kr; jd03@etri.re.kr).

C.-S. Park is with the Department of Information and Communications,

Gwangju Institute of Science and Technology, Buk-gu, Gwangju 500-712,

Korea.

Color versions of one or more of the figures in this letter are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LPT.2010.2091122

Fig. 1. The 2.5-Gb/s burst-mode receiver architecture.

on the optical receiver design at the OLT side, for example,

high sensitivity, wide dynamic range, and rapid detection to the

burst-mode input data, etc. The burst-mode optical receivers are

mainly fabricated in InP/InGaAs heterojunction bipolar transistor

(HBT), SiGe bipolar complementary metal–oxide–semiconductor

(BiCMOS), or Si complementary metal-oxide semiconductor

(CMOS) technologies [1]–[6].

In this letter, we suggest a state-of-the-art burst-mode receiver

with burst detection function, which has high sensitivity

and wide dynamic range for various classes of power budgets

with Forward Error Correction (FEC) required in XG-PON1.

The new 2.5 Gb/s burst-mode receiver has been fabricated for a

single chip with transimpedance and limiting amplifiers using

0.25 m SiGe BiCMOS technology.

II. SINGLE-CHIP BURST-MODE RECEIVER ARCHITECTURE

AND RECEIVER DESIGN

A. Burst-Mode Optical Receiver Architecture

The architecture of a single-chip burst-mode optical receiver

is shown in Fig. 1. The transimpedance amplifier (TIA) converts

and amplifies current signal from the photodiode to singleended

voltage signal, the single-to-differential converter (S2D)

generates differential outputs, the AOC (automatic offset cancellation)

amplifies the signal with automatic offset compensation

function, and the output buffer (BUF) provides CML (current-

mode logic) output level matched to 50 . An on-chip bias

circuit generates the bias voltage for S2D and the AGC (automatic

gain control) trigger also uses this bias voltage as a reference,

which generates control signal (AGC signal) to lower gain

of TIA at the beginning of a burst when input signal is strong.

A squelch circuit is used to release the settled preamble output

after the AOC process, which is helpful for correct phase alignment

during the CDR (clock-data-recovery) locking time. Timer

block generates control signals for triggers, AOC, and squelch

blocks.

On the other hand, as the exact time slot of ONU is not known

under ranging period for the general case, the reset pulse ends

1041-1135/$26.00 © 2010 IEEE

86 IEEE PHOTONICS TECHNOLOGY LETTERS, VOL. 23, NO. 2, JANUARY 15, 2011

Fig. 2. TIA circuit.

Fig. 3. AGC trigger circuit.

before burst arrives. However, the AOC reset needs to be at the

beginning of a burst. Therefore, the receiver should have a burst

detect function to find the appearance of burst and start AOC

reset. It is accomplished by the burst detect trigger connected at

S2D outputs. The result of burst detection enables the AGC operation

and starts the timer for AOC reset after a certain period.

It also sets the timer for squelch function of outputs.

B. Burst-Mode Optical Receiver Integrated Circuits Design

Because the TIA determines noise level of the whole receiver,

it should have low noise. TIA block uses common-emitter gain

stage for best noise performance, whose schematic is given

in Fig. 2. Main gain stage is transistor Q1 and I1 as a current

source. Transistor Q2 is the emitter follower providing low

output impedance, with a current source I2. Then the feedback

network is connected between base of Q1 and emitter of Q2.

Dynamic range is extended by using AGC function. For fast

response, we adopt TIA with one-step AGC. The TIA has 2

gain modes, which are high gain (AGC OFF) when input signal

is weak and low gain (AGC ON) when input signal is strong.

At high gain mode, switch M2 is open and therefore feedback

resistor is RF1. At low gain mode, the M2 switch is closed by

AGC signal, the feedback resistor is RF1//RF2 and has lower

value than RF1, thereby reducing the gain of the TIA.

Fig. 3 shows AGC trigger circuit. The AGC trigger compares

the difference between the TIA output and the on-chip reference

bias output and quickly switches the TIA to lower gain at the

beginning of a burst by digitized AGC signal when input signal

Fig. 4. AOC circuit with limiting amplifier.

Fig. 5. Photograph of a single-chip 2.5-Gb/s burst-mode optical receiver.

is strong. The AGC trigger can’t turn off once it is turned on by

strong input signal, until reset signal is applied. Transistor M1 is

a switch to pull up the base of Q3 to high voltage when reset is

applied.With Q3 turn on, the positive feedback loop changes the

polarity of the outputs to OFF state. And when reset is finished,

the trigger is at initial condition, ready to detect new burst.

Burst Detect Trigger detects the appearance of signal to mark

the beginning of a burst. This trigger is supposed to turn on at

every burst with power higher than the sensitivity level. Therefore

the trigger should be rather sensitive and need amplification

before entering the trigger. Consequently, the Burst Detect

Trigger is connected at the outputs of S2D and can only switch to

ON during burst. After burst, external reset changes the trigger

to initial condition. The trigger shares the same circuit with the

AGC trigger (Fig. 3) and just the ratio is changed for more detection

sensitivity.

The AOC circuit with limiting amplifier (LA) is shown in

Fig. 4. The emitter followers Q1, Q2 and capacitors C1, C2 act

as peak level detectors of signals at inputs In1 and In2 of the

AOC circuit. The AOC circuit of and in cascode configuration

with and is the same as the main amplifier

M1 and M2 in cascode configuration with M3 and M4, which

share the same load (RL1, RL2). The AOC circuit and the main

amplifier have the same gain. After offset is cancelled at the

output of AOC circuit, the signal is then fed to a normal differential

gain stage for amplification. The gain stage consists of

cascode pairs Q5, Q6 and Q7, Q8 with load pair RL3 and RL4.

Also, in Fig. 4, the peak detection is reset after every burst to

return to initial condition. Reset signal is the AOC reset signal

in block diagram in Fig. 1. When AOC reset is HIGH, M5 and

M6 is closed, providing path to discharge C1 and C2 to ground.

III. FABRICATION AND MEASUREMENT

The single-chip 2.5 Gb/s burst-mode receiver size is 1.1 mm

1.3 mm as shown in Fig. 5 and has been assembled on a

TO-46 package with an avalanche photodiode (APD) to measure

the state-of-the-art performance of a 2.5 Gb/s burst-mode

receiver. The active area and response of APD chip are typically

50 m and 0.9 A/W (@1310 nm), and ROSA (receiver

LEE et al.: A SINGLE-CHIP 2.5-Gb/s BURST-MODE OPTICAL RECEIVER WITH WIDE DYNAMIC RANGE 87

Fig. 6. Waveforms of optical input (top) and electrical output (bottom) for

2.5-Gb/s burst-mode optical receiver.

Fig. 7. BER performances and eye patterns of 2.5-Gb/s burst-mode optical receiver

with APD.

optical subassembly) type of the receiver module has been used

for testing of the chip performances.

The bit error rate (BER) and output waveform of the burstmode

receiver have been evaluated in an experimental setup

with two GPON optical network terminals (ONTs) set at extremely

different input powers at the receiver end.

Based on the G.987.2 objective specification for 2.5 Gb/s upstream,

recommended allocation of burst-mode overhead time

for XG-PON1 OLT function is consisted with 64 bits guard

time, 160 bits preamble time and 32 bits delimiter. A 1.25 Gb/s

burst-mode clock phase aligner (CPA) chip in the current GPON

market requires a maximum of 13 bits to clock, and no burstmode

CPA/CDR chip for 2.5 Gb/s XG-PON1 is commercially

available at this time. We use a conservative estimate of a minimum

96-bit locking time for a 2.5 Gb/s GPON CDR, which

results in 64 bits, equalling 25.6 ns of settling time in our design

target.

Fig. 6 shows waveform of receiver electrical output for

2.5 Gb/s burst optical input. The each received optical inputs

from ONT1 and ONT 2 are 8 dBm and 28 dBm, while

the guard time between two ONTs is 64 bits and the preamble

input of ONT2 is 128 bits in the measurement. The electrical

waveform of receiver output shows that the settling time after

squelch is less than 25 ns.

The BER and eye pattern have been evaluated using various

input power levels for ONT1 while ONT2 is maintained within

a fixed level for the worst case of power difference. As shown in

Fig. 7, the sensitivity and overload performance are 32 dBm

and 4 dBm at a BER of , which indicates 28 dB of

wide dynamic range or loud/soft ratio between ONTs. The wide

dynamic range obtained for 2.5 Gb/s burst-mode receiver with

one-step AGC is compared with the best performance of previ-

TABLE I

PERFORMANCE SUMMARY FOR 2.5-Gb/s BURST-MODE OPTICAL RECEIVER

ously published 1.25 Gb/s burst-mode receiver, as compared in

Table I. The eye diagrams inserted in Fig. 7 represent the electrical

bit patterns between preamble and payload, and have been

measured at sensitivity and overload power levels respectively.

The pulse width for ‘1’ level is in the range of 370 400 ps

through the input signal power variation from sensitivity to overload

(The input signal power dependence of the duty cycle of ‘1’

level is from 46% to 50%).

The operating current of burst-mode receiver is less than

56 mA at 3.3 V. The main increase of power consumption

of proposed technology against the technology which was

proposed in [4] results from the introduction of Burst Detect

Trigger to find the appearance of burst. This burst-mode receiver

has strong BER endurance for the bias variation in 3.3

0.15 V and the operating temperature from 0 to 75 C.

IV. CONCLUSION

In this letter, a state-of-the-art 2.5 Gb/s burst-mode receiver

with burst detection function has been presented and a single

receiver chip with transimpedance and limiting amplifiers has

been fabricated. The burst-mode optical receiver with an APD

has high sensitivity and wide dynamic range for various classes

of power budges required in XG-PON1. For the 2.5 Gb/s burstmode

data streams, sensitivity and overload are 32 dBm and

4 dBm at a bit error rate of , respectively, resulting in a

dynamic range of 28 dB. This wide dynamic range obtained by

using fast one-step AGC satisfies the recommended burst-mode

overhead time for XG-PON1 OLT function.

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